`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/10/29 12:13:55
// Design Name: 
// Module Name: my_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module my_tb;
    reg   [11:0] contr;
    reg   [31:0] op1,op2;   
    wire  [31:0] result;
    wire cout;
    
    my_alu alu(
        .contr(contr),
        .op1(op1),
        .op2(op2),
        .cout(cout),
        .result(result)
    );
    
    initial begin  contr=1'b0;  end

    always 
    begin
        #10 op1<=32'h1111abbb; 
            op2<=32'haaab1111;
            contr<=4'd1;
        #10 op1<=32'habbb; 
            op2<=32'h1111;
            contr<=4'd2;
        #10 op1<=32'h11110000; 
            op2<=32'haaab1111;
            contr<=4'd3;  
        #10 contr<=4'd4;
        #10 contr<=4'd5;
        #10 contr<=4'd6;
        #10 contr<=4'd7;
        #10 contr<=4'd8;
        #10 contr<=4'd9;
        #10 contr<=4'ha;
        #10 contr<=4'hb;
        #10 contr<=4'hc;
    end

endmodule
